> + - spread-spectrum: SSC mode as defined in the data sheet. > +spectrum clocking parameters for a board. > +For both PLL1 and PLL2 an optional child node can be used to specify spread > + board, or to compensate for external influences. > + - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a > + - #clock-cells: From common clock bindings: Shall be 1. > + - clocks: Points to a fixed parent clock that provides the input frequency.
#Unable to init the driver clogkgen driver
> +The driver provides clock sources for each output Y1 through Y5. > + Documentation/devicetree/bindings/clock/clock-bindings.txt > +This binding uses the common clock binding. > -0,0 +1,42 +Binding for TO CDCE925 programmable I2C clock synthesizers. > +++ b/Documentation/devicetree/bindings/clock/ti,cdce925.txt > diff -git a/Documentation/devicetree/bindings/clock/ti,cdce925.txt b/Documentation/devicetree/bindings/clock/ti,cdce925.txt > create mode 100644 drivers/clk/clk-cdce925.c > create mode 100644 Documentation/devicetree/bindings/clock/ti,cdce925.txt devicetree/bindings/clock/ti,cdce925.txt | 42 ++ > v4: Fix dev_dbg format warning on 64-bit systems (as suggested by Paul Bolle) > v3: Remove clk-private.h and processed M.Turquette's feedback > divider to best approximate the desired output. > Given a target output frequency, the driver will set the PLL and > and uses a fixed setting for the output muxes: The driver only supports the following setup, > The chip contains two PLLs with spread-spectrum clocking support and > This driver supports the TI CDCE925 programmable clock synthesizer.